The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 09, 2016

Filed:

Sep. 03, 2013
Applicant:

Cirrus Logic, Inc., Austin, TX (US);

Inventors:

Tejasvi Das, Austin, TX (US);

Alvin C. Storvik, Austin, TX (US);

Assignee:

Cirrus Logic, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/087 (2006.01); H03L 7/093 (2006.01); H03L 7/14 (2006.01); H03L 7/10 (2006.01); H03L 7/107 (2006.01);
U.S. Cl.
CPC ...
H03L 7/148 (2013.01); H03L 7/087 (2013.01); H03L 7/093 (2013.01); H03L 7/103 (2013.01); H03L 7/105 (2013.01); H03L 7/1075 (2013.01); H03L 7/146 (2013.01); H03L 2207/06 (2013.01);
Abstract

An oscillator of a phase-locked loop (PLL) or frequency-locked loop (FLL) may include two inputs. The two inputs may include a first analog input and a second digital input. The second digital input may receive a digital signal setting a desired output clock frequency of the oscillator and/or indicating an approximate frequency of frequency range for output by the oscillator. The first analog input may receive a voltage representative of a desired frequency for the output clock frequency of the PLL or FLL to fine-tune the output frequency from the approximate frequency set by the second digital input. The first analog input may be generated from a master clock input signal. When the master clock input signal disappears, the second digital signal controls the output frequency of the oscillator to allow redundant operation of the PLL or FLL even when no master clock input signal is present.


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