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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9257984 B1

PDFFull Text
Date of Patent:
Feb. 09, 2016

Filed:

Sep. 16, 2014

Multi-threshold circuitry based on silicon-on-insulator technology

Applicant:

Wave Semiconductor, Inc., Sunnyvale, CA (US);

Inventors:

Gajendra Prasad Singh, Sunnyvale, CA (US);

Roger Carpenter, Palo Alto, CA (US);

Assignee:

Wave Semiconductor, Inc., Campbell, CA (US);

Attorney:

Adams Intellex, PLC

Primary Examiner:

Phuc Dang

Int. Cl.
CPC ...
H01L 27/10 (2006.01); H03K 19/0948 (2006.01); H01L 27/12 (2006.01); G06F 17/50 (2006.01); H01L 21/84 (2006.01); H03K 19/08 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
H03K 19/0948 (2013.01); G06F 17/505 (2013.01); G06F 17/5072 (2013.01); H01L 21/84 (2013.01); H01L 27/1203 (2013.01); H03K 19/0813 (2013.01); H03K 19/20 (2013.01);
Abstract

Multiple threshold voltage circuitry based on silicon-on-insulator (SOI) technology is disclosed which utilizes N-wells and/or P-wells underneath the insulator in SOI FETs. The well under a FET is biased to influence the threshold voltage of the FET. A PFET and an NFET share a common buried P-well or N-well. Various types of logic can be fabricated in silicon-on-insulator (SOI) technology using multiple threshold voltage FETs. Embodiments provide circuits including the advantageous properties of both low-leakage transistors and high-speed transistors.

Find Patent Forward Citations

Singh, Gajendra. (2016). Multi-threshold circuitry based on silicon-on-insulator technology (U.S. Patent No. 9257984). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9257984

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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