The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 09, 2016
Filed:
Oct. 23, 2009
Klaus-peter Saeck, Detmold, DE;
Thomas Warneke, Hoexter, DE;
Viktor Oster, Blomberg, DE;
Abstract
The invention is based on the problem of devising a circuit arrangement () for protecting electronic devices from incorrect logic voltages, wherein this circuit arrangement delivers increased protection against overvoltages, so that this circuit arrangement could also be used in multi-channel fail-safe systems that satisfy, for example, Performance Level 'e' according to DIN EN ISO 13849. The circuit arrangement () has an input terminal () for connecting a power supply device and at least one voltage converter () that delivers, on the output side, an adjustable logic voltage. A controllable switching element () is connected between the one or more voltage converters () and the input terminal (). Furthermore, a first monitoring device () is provided for monitoring the logic voltage. The first monitoring device () is constructed so that it triggers the opening of the switching element () when the logic voltage reaches or exceeds a predetermined threshold.