The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 09, 2016
Filed:
Apr. 17, 2014
Applicant:
Stmicroelectronics (Crolles 2) Sas, Crolles, FR;
Inventors:
Assignee:
STMicrolectronics (Crolles 2) SAS, Crolles, FR;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 29/423 (2006.01); H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 21/28 (2006.01); H01L 29/49 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42372 (2013.01); H01L 21/28079 (2013.01); H01L 21/28088 (2013.01); H01L 21/8234 (2013.01); H01L 27/088 (2013.01); H01L 29/4966 (2013.01); H01L 29/78 (2013.01);
Abstract
At least one MOS transistor is produced by forming a dielectric region above a substrate and forming a gate over the dielectric region. The gate is formed to include a metal gate region. Formation of the metal gate region includes: forming a layer of a first material configured to reduce an absolute value of a threshold voltage of the transistor, and configuring a part of the metal gate region so as also to form a diffusion barrier above the layer of the first material. Then, doped source and drain regions are formed using a dopant activation anneal.