The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 09, 2016
Filed:
Mar. 04, 2015
Applicant:
SK Hynix Inc., Icheon, KR;
Inventor:
Min Chul Sung, Seoul, KR;
Assignee:
SK HYNIX INC., Icheon, KR;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 21/8234 (2006.01); H01L 23/525 (2006.01); H01L 21/66 (2006.01); H01L 27/112 (2006.01); H01L 27/118 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823475 (2013.01); H01L 22/22 (2013.01); H01L 23/5252 (2013.01); H01L 27/11206 (2013.01); H01L 27/11803 (2013.01); H01L 2924/0002 (2013.01);
Abstract
An anti-fuse array of a semiconductor device and a method for forming the same are disclosed. The anti-fuse array for a semiconductor device includes a first-type semiconductor substrate formed to define an active region by a device isolation region, a second-type impurity implantation region formed in the active region, a first-type channel region isolated from the semiconductor substrate by the second-type impurity implantation region, a gate electrode formed over the channel region, and a first metal contact formed over the second-type impurity implantation region.