The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 09, 2016

Filed:

Jul. 01, 2015
Applicant:

Renesas Electronics Corporation, Kawasaki-shi, JP;

Inventors:

Hiroyuki Takahashi, Kawasaki, JP;

Masahiro Yoshida, Kawasaki, JP;

Assignee:

RENESAS ELECTRONICS CORPORATION, Kawasaki-Shi, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/4096 (2006.01); G11C 11/4094 (2006.01); G11C 11/4091 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4094 (2013.01); G11C 11/4091 (2013.01); G11C 11/4096 (2013.01);
Abstract

A semiconductor memory device, including a plurality of pairs of bit lines; a plurality of memory cells coupled to a plurality of word lines and the plurality of pairs of bit lines; a plurality of sense amplifiers each coupled between a corresponding pair of bit lines; a plurality of first driver transistors coupled between at least one of the sense amplifiers and a first power supply line; a plurality of second driver transistors coupled between at least two of the sense amplifiers and a second power supply line; a pair of common data lines; a plurality of column selection gates each coupled between a corresponding one of pair of bit lines and a corresponding one of pair of common data lines, and a plurality of mask selection gates each coupled between a corresponding one of pair of bit lines and a corresponding one of column selection gates.


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