The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 09, 2016

Filed:

May. 08, 2013
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Scott Ricketts, San Francisco, CA (US);

Luke David Durant, Santa Clara, CA (US);

Brian Scott Pharris, Cary, NC (US);

Igor Sevastiyanov, San Jose, CA (US);

Nicholas Wang, Saratoga, CA (US);

Assignee:

NVIDIA Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 7/00 (2006.01); G06F 17/30 (2006.01); G06F 9/52 (2006.01);
U.S. Cl.
CPC ...
G06F 17/30292 (2013.01); G06F 9/52 (2013.01); G06F 17/30289 (2013.01);
Abstract

A system, method, and computer program product for scheduling tasks associated with continuation thread blocks. The method includes the steps of generating a first task metadata data structure in a memory, generating a second task metadata data structure in the memory, executing a first task corresponding to the first task metadata data structure in a processor, generating state information representing a continuation task related to the first task and storing the state information in the second task metadata data structure, executing the continuation task in the processor after the one or more child tasks have finished execution, and indicating that the first task has logically finished execution once the continuation task has finished execution. The second task metadata data structure is related to the first task metadata data structure, and at least one instruction in the first task causes one or more child tasks to be executed by the processor.


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