The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 09, 2016

Filed:

Nov. 13, 2014
Applicant:

Oracle International Corporation, Redwood City, CA (US);

Inventors:

Hiren D. Thacker, San Diego, CA (US);

Ashok V. Krishnamoorthy, San Diego, CA (US);

Robert David Hopkins, II, Foster City, CA (US);

Jon Lexau, Beaverton, OR (US);

Ronald Ho, Mountain View, CA (US);

John E. Cunningham, San Diego, CA (US);

Assignee:

ORACLE INTERNATIONAL CORPORATION, Redwood Shores, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02B 6/12 (2006.01); G02B 6/42 (2006.01);
U.S. Cl.
CPC ...
G02B 6/12 (2013.01); G02B 6/4274 (2013.01);
Abstract

A chip package includes an optical integrated circuit (such as a hybrid integrated circuit) and an integrated circuit that are adjacent to each other on the same side of a substrate in the chip package. The integrated circuit includes electrical circuits, such as memory or a processor, and the optical integrated circuit communicates optical signals with very high bandwidth. In addition, an input/output (I/O) integrated circuit is coupled to the optical integrated circuit between the substrate and the optical integrated circuit. This I/O integrated circuit includes high-speed I/O circuits and energy-efficient driver and receiver circuits and communicates with optical devices on the optical integrated circuit. By integrating the optical integrated circuit, the integrated circuit and the I/O integrated circuit in close proximity, the chip package may facilitate improved performance compared to chip packages with electrical interconnects.


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