The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2016

Filed:

Oct. 21, 2011
Applicants:

Jasson Flinn, Ottawa, CA;

Juan-carlos Calderon, Fremont, CA (US);

Jean-michel Caia, Plymouth, CA (US);

Arun Zarabi, Sacramento, CA (US);

Scott Feller, Mountain View, CA (US);

Inventors:

Jasson Flinn, Ottawa, CA;

Juan-Carlos Calderon, Fremont, CA (US);

Jean-Michel Caia, Plymouth, CA (US);

Arun Zarabi, Sacramento, CA (US);

Scott Feller, Mountain View, CA (US);

Assignee:

Cortina Systems, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04J 3/06 (2006.01); H04L 12/26 (2006.01);
U.S. Cl.
CPC ...
H04J 3/0667 (2013.01); H04J 3/0673 (2013.01); H04L 43/0852 (2013.01); H04L 43/106 (2013.01);
Abstract

Despite a recent revision, IEEE 1588™-2008 does not provide a complete implementation for PTP (precision time protocol) that accounts for variable delays introduced by network components. According to a broad aspect, the present disclosure provides implementations that account for variable delays introduced by network components. Therefore, the amount of time that a packet spends in transit through a transparent clock can be accounted for. According to another broad aspect, there is provided a master-slave mode that allows a transparent clock to function as a master or a slave to another clock.


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