The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2016

Filed:

Mar. 28, 2014
Applicant:

Silicon Graphics International Corp., Milpitas, CA (US);

Inventors:

Mark Ronald Sikkink, Chippewa Falls, WI (US);

John Francis De Ryckere, Eau Claire, WI (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/00 (2006.01); H03M 13/17 (2006.01); H03M 13/09 (2006.01); H04L 1/00 (2006.01); H03M 13/11 (2006.01);
U.S. Cl.
CPC ...
H03M 13/17 (2013.01); H03M 13/09 (2013.01); H03M 13/11 (2013.01); H04L 1/0057 (2013.01); H04L 1/0061 (2013.01);
Abstract

A high performance computing system and method communicate data packets between computing nodes on a multi-lane communications link using a modified header bit encoding. Each data packet is provided with flow control information and error detection information, then divided into per-lane payloads. Sync header bits for each payload are added to the payloads in non-adjacent locations, thereby decreasing the probability that a single correlated burst error will invert both header bits. The encoded blocks that include the payload and the interspersed header bits are then simultaneously transmitted on the multiple lanes for reception, error detection, and reassembly by a receiving computing node.


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