The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2016

Filed:

Dec. 22, 2014
Applicants:

Anand Kumar Sinha, Noida, IN;

Deependra K. Jain, Noida, IN;

Krishna Thakur, Greater Noida, IN;

Inventors:

Anand Kumar Sinha, Noida, IN;

Deependra K. Jain, Noida, IN;

Krishna Thakur, Greater Noida, IN;

Assignee:

FREESCALE SEMICONDUCTOR,INC., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01); H03L 7/099 (2006.01);
U.S. Cl.
CPC ...
H03L 7/099 (2013.01);
Abstract

A phase locked loop (PLL) system generates an oscillator signal by providing a fixed control voltage to a programmable voltage to current converter having switch selection inputs and a variable current output. Logic values are provided to the switch selection inputs to adjust a control current at the variable current output and a frequency of the oscillator signal is adjusted based on the control current. The logic values are fixed when a first condition is reached, which is based on the frequency of the oscillator signal, a division factor, and an input reference signal frequency. The fixed control voltage provided to the programmable voltage to current converter is then replaced with a charge pump control voltage based on an error signal. The error signal is based on a comparison of the input reference signal frequency and a fraction of the oscillating frequency.


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