The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2016

Filed:

May. 27, 2013
Applicants:

Sunny Gupta, Noida, IN;

Kumar Abhishek, Ghaziabad, IN;

Nitin Pant, New Delhi, IN;

Garima Sharda, Ghaziabad, IN;

Inventors:

Sunny Gupta, Noida, IN;

Kumar Abhishek, Ghaziabad, IN;

Nitin Pant, New Delhi, IN;

Garima Sharda, Ghaziabad, IN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/26 (2006.01); H03K 19/00 (2006.01); G06F 1/32 (2006.01);
U.S. Cl.
CPC ...
H03K 19/0016 (2013.01); G06F 1/32 (2013.01); G06F 1/26 (2013.01); G06F 1/3287 (2013.01);
Abstract

An integrated circuit (IC) that operates in high and low power modes includes high and low power regulators, first and second sets of circuits, a switch connecting the high power regulator and the second set of circuits, and a wake-up control system. The wake-up control system includes a state machine that enables the high power regulator when the IC is in the high power mode, and enables the low power regulator when the IC is in the low power mode. The switch is closed when the high power regulator reaches a first threshold voltage. The state machine operates on a low frequency clock signal when the IC is in the low power mode and during wake-up, and on a high frequency clock signal in the high power mode after the switch is closed.


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