The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2016

Filed:

Dec. 20, 2013
Applicant:

Telefonaktiebolaget L M Ericsson (Publ), Stockholm, SE;

Inventors:

Bi Pham, Ottawa, CA;

Somsack Sychaleun, Ottawa, CA;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/68 (2006.01); H03F 1/56 (2006.01); H03F 1/02 (2006.01); H03F 1/48 (2006.01); H03F 3/60 (2006.01); H03F 3/21 (2006.01);
U.S. Cl.
CPC ...
H03F 1/56 (2013.01); H03F 1/0288 (2013.01); H03F 1/48 (2013.01); H03F 3/211 (2013.01); H03F 3/602 (2013.01); H03F 2200/36 (2013.01); H03F 2200/405 (2013.01); H03F 2200/408 (2013.01); H03F 2203/21139 (2013.01); H03F 2203/21142 (2013.01);
Abstract

The output of a carrier amplifier circuit in a Doherty amplifier is coupled to the summing node so that the impedance observed by the carrier amplifier's output is approximately equal to the load impedance at the combining node when the load impedance is not modulated. In an example non-inverting configuration, a power amplifier circuit is configured to provide an amplified signal to a load at a summing node, where the load has a first impedance when not load-modulated. The power amplifier circuit includes a splitter network arranged to receive the input signal and to split the input signal to provide a carrier input signal and a peaking input signal, a carrier amplifier path configured to amplify the carrier input signal in a full-power mode and in a first backoff mode, and a peaking amplifier path configured to amplify the peaking input signal in at least the full-power mode.


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