The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 02, 2016
Filed:
May. 10, 2013
Yan LI, Cambridge, MA (US);
Zhipeng LI, Cambridge, MA (US);
Yehuda Avniel, Cambridge, MA (US);
Alexandre Megretski, Concord, MA (US);
Vladimir Marko Stojanovic, Lexington, MA (US);
Yan Li, Cambridge, MA (US);
Zhipeng Li, Cambridge, MA (US);
Yehuda Avniel, Cambridge, MA (US);
Alexandre Megretski, Concord, MA (US);
Vladimir Marko Stojanovic, Lexington, MA (US);
Massachusetts Institute of Technology, Cambridge, MA (US);
Abstract
Described herein is a fixed-point piece-wise linear (FP PWL) approximation technique for computations of nonlinear functions. The technique results in circuit designs having relatively few and simple arithmetic operations, short arithmetic operands and small-sized look-up tables and the circuits resultant there from can be efficiently pipelined to run at multi-GSamples/s throughputs. In one exemplary embodiment, the FP PWL approximation technique was used in the design of an energy-efficient high-throughput and high-precision signal component separator (SCS) for use with in an asymmetric-multilevel-outphasing (AMO) power amplifier. The FP PWL approximation technique is appropriate for use in any application requiring high-throughput, area and power constrained hardware implementations of nonlinear functions.