The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2016

Filed:

Feb. 18, 2014
Applicant:

Samsung Display Co., Ltd., Yongin, KR;

Inventors:

Jong-Chan Lee, Suwon-si, KR;

Yoon-Ho Khang, Yongin-si, KR;

Su-Hyoung Kang, Bucheon-si, KR;

Dong-Jo Kim, Yongin-si, KR;

Ji-Seon Lee, Hwaseong-si, KR;

Myoung-Geun Cha, Seoul, KR;

Deuk-Myung Ji, Hwaseong-si, KR;

Assignee:

Samsung Display Co., Ltd., Yongin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7869 (2013.01); H01L 29/66969 (2013.01); H01L 29/78606 (2013.01); H01L 29/78618 (2013.01); H01L 29/78693 (2013.01);
Abstract

A display substrate and a method for manufacturing a display substrate are disclosed. In the method, a gate electrode is formed on a base substrate. An active pattern is formed using an oxide semiconductor. The active pattern partially overlaps the gate electrode. A first insulation layer pattern and a second insulation layer pattern are sequentially formed on the active pattern. The first insulation layer pattern and the second insulation layer pattern overlap the gate electrode. A third insulation layer is formed to cover the active pattern, the first insulation layer pattern and the second insulation layer pattern. Either the first insulation layer pattern or the second insulation layer pattern includes aluminum oxide. Forming the first insulation layer pattern and the second insulation layer pattern includes performing a backside exposure process using the gate electrode as an exposure mask.


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