The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2016

Filed:

Sep. 19, 2013
Applicant:

Electronics and Telecommunications Research Institute, Daejeon, KR;

Inventors:

Him Chan Oh, Seoul, KR;

Chi Sun Hwang, Daejeon, KR;

Sang Hee Park, Daejeon, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/786 (2006.01); H01L 29/45 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66742 (2013.01); H01L 29/45 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01);
Abstract

Disclosed are a self-aligned thin film transistor capable of simultaneously improving an operation speed and stability and minimizing a size thereof by forming source and drain electrodes so as to be self-aligned, and a fabrication method thereof. The method of fabricating a thin film transistor according to an exemplary embodiment of the present disclosure includes: forming an active layer, a gate insulator, and a gate layer on a substrate; forming a photoresist layer pattern for defining a shape of a gate electrode on the gate layer; etching the gate layer, the gate insulator, and the active layer by using the photoresist layer pattern; depositing a source and drain layer on the etched substrate by a deposition method having directionality; and forming a gate electrode and self-aligned source electrode and drain electrode by removing the photoresist layer pattern.


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