The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2016

Filed:

Feb. 28, 2013
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Roger A. Booth, Wappingers Falls, NY (US);

Lawrence A. Clevenger, LaGrangeville, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/30 (2006.01); H01L 49/02 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 28/20 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 21/76808 (2013.01); H01L 21/76831 (2013.01); H01L 23/5228 (2013.01); H01L 23/5329 (2013.01); H01L 23/53295 (2013.01); H01L 28/24 (2013.01); H01L 2924/0002 (2013.01); H01L 2924/12044 (2013.01); Y10T 29/4913 (2015.01); Y10T 29/49082 (2015.01); Y10T 29/49155 (2015.01);
Abstract

A stack of an interconnect-level dielectric material layer and a disposable dielectric material layer is patterned so that at least one recessed region is formed through the disposable dielectric material layer and in an upper portion of the interconnect-level dielectric material layer. A dielectric liner layer and a metallic liner layer is formed in the at least one recessed region. At least one photoresist is applied to fill the at least one recessed region and lithographically patterned to form via cavities and/or line cavities in the interconnect-level dielectric material layer. After removing the at least one photoresist, the at least one recessed region, the via cavities, and/or the line cavities are filled with at least one metallic material, which is subsequently planarized to form at least one planar resistor having a top surface that is coplanar with top surfaces of metal lines or metal vias.


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