The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9252104 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 02, 2016

Filed:

Oct. 10, 2014
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

John J. Zhu, San Diego, CA (US);

Bin Yang, San Diego, CA (US);

Pr Chidambaram, San Diego, CA (US);

Lixin Ge, San Diego, CA (US);

Jihong Choi, San Diego, CA (US);

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/00 (2006.01); H01L 23/538 (2006.01); H01L 27/08 (2006.01); H01L 49/02 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 23/538 (2013.01); H01L 23/5223 (2013.01); H01L 27/0805 (2013.01); H01L 28/40 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A complementary back end of line (BEOL) capacitor (CBC) structure includes a metal oxide metal (MOM) capacitor structure. The MOM capacitor structure is coupled to a first upper interconnect layer of an interconnect stack of an integrated circuit (IC) device. The MOM capacitor structure includes a lower interconnect layer of the interconnect stack. The CBC structure also includes a second upper interconnect layer of the interconnect stack coupled to the MOM capacitor structure. The CBC structure also includes a metal insulator metal (MIM) capacitor layer between the first upper interconnect layer and the second upper interconnect layer. In addition, CBC structure also includes a MIM capacitor structure coupled to the MOM capacitor structure. The MIM capacitor structure includes a first capacitor plate having a portion of the first upper interconnect layer, and a second capacitor plate having a portion of the MIM capacitor layer(s).


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