The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2016

Filed:

Feb. 10, 2015
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Karl R. Erickson, Rochester, MN (US);

Phil C. Paone, Rochester, MN (US);

David P. Paulsen, Inver Grove Heights, MN (US);

John E. Sheets, II, Zumbrota, MN (US);

Gregory J. Uhlmann, Rochester, MN (US);

Kelly L. Williams, Austin, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 27/112 (2006.01); H01L 23/525 (2006.01); H01L 21/74 (2006.01); H01L 21/66 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 21/743 (2013.01); H01L 22/32 (2013.01); H01L 23/5252 (2013.01); H01L 24/13 (2013.01); H01L 27/11206 (2013.01); H01L 2224/13025 (2013.01);
Abstract

A semiconductor chip includes a substrate having a frontside and a backside coupled to a ground. The chip includes a circuit in the substrate at the frontside. A through silicon via (TSV) having a front-end, a back-end, and a lateral surface is included. The back-end and lateral surface of the TSV are in the substrate, and the front-end of the TSV is substantially parallel to the frontside of the substrate. The chip also includes an antifuse material deposited between the back-end and lateral surface of the TSV and the substrate. The antifuse material insulates the TSV from the substrate. The chip includes a ground layer insulated from the substrate and coupled with the TSV and the circuit. The ground layer conducts a program voltage to the TSV to cause a portion of the antifuse material to migrate away from the TSV, thereby connecting the circuit to the ground.


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