The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2016

Filed:

Sep. 26, 2014
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Wenqing Wu, San Diego, CA (US);

Kendrick Hoy Leong Yuen, San Diego, CA (US);

Karim Arabi, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/18 (2006.01); G11C 11/16 (2006.01); G11C 14/00 (2006.01); H03K 19/18 (2006.01); H03K 3/356 (2006.01); H03K 3/59 (2006.01); H03K 3/3562 (2006.01);
U.S. Cl.
CPC ...
G11C 11/1693 (2013.01); G11C 11/16 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); G11C 11/18 (2013.01); G11C 14/0081 (2013.01); H03K 3/356008 (2013.01); H03K 3/59 (2013.01); H03K 19/18 (2013.01); H03K 3/35625 (2013.01);
Abstract

Systems and methods are directed to a single-phase non-volatile flip-flop (NVFF), which includes a master stage formed from a dual giant spin Hall effect (GSHE)-magnetic tunnel junction (MTJ) structure, the dual GSHE-MTJ structure comprising a first GSHE-MTJ and a second GSHE-MTJ coupled between a first combined terminal and a second combined terminal, and a slave stage formed from a first inverter coupled to a second inverter. During a single clock cycle of a clock, a first data value is read out from the slave stage when a clock is in a high state and a second data value is written into the master stage, when the clock is in a low state. The first and second inverters are cross coupled in a latch configuration to hold the first data value as an output, when the clock is in the low state.


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