The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2016

Filed:

Apr. 05, 2012
Applicants:

Ping-sheng Kuo, Hsin-Chu, TW;

Hsiang-lin Lin, Hsin-Chu, TW;

Chih-cheng Chan, Hsin-Chu, TW;

Sheng-wen Huang, Hsin-Chu, TW;

Inventors:

Ping-Sheng Kuo, Hsin-Chu, TW;

Hsiang-Lin Lin, Hsin-Chu, TW;

Chih-Cheng Chan, Hsin-Chu, TW;

Sheng-Wen Huang, Hsin-Chu, TW;

Assignee:

AU OPTRONICS CORP., Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 3/34 (2006.01);
U.S. Cl.
CPC ...
G09G 3/344 (2013.01); G09G 2310/0275 (2013.01); G09G 2310/0281 (2013.01);
Abstract

An electrophoretic display apparatus and an image-updating method thereof are provided. The electrophoretic display apparatus comprises a display panel and a source driver. The display panel comprises a plurality of pixels and a plurality of source lines, and each pixel electrode is electrically coupled to an AC common voltage through a corresponding capacitor. The capacitor comprises a plurality of charged particles. The source driver comprises a first data-latching circuit and a second data-latching circuit. Each of the data-latching circuits comprises a transistor, a capacitor and an inverter. The first data-latching circuit receives image data and a data shift-register output pulse. The second data-latching circuit is electrically coupled between an output terminal of the first data-latching circuit and a source line and is used for receiving a data output pulse.


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