The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2016

Filed:

Sep. 19, 2013
Applicant:

Marvell International Ltd., Hamilton, BM;

Inventors:

Siu-Hung Fred Au, Fremont, CA (US);

Gregory Burd, San Jose, CA (US);

Wayne C. Datwyler, Mission Viejo, CA (US);

Leonard J. Galasso, Trabuco Canyon, CA (US);

Tze Lei Poo, Cambridge, MA (US);

Minda Zhang, Westford, MA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/14 (2006.01); G06F 21/78 (2013.01); G06F 21/72 (2013.01); G06F 21/85 (2013.01);
U.S. Cl.
CPC ...
G06F 21/78 (2013.01); G06F 21/72 (2013.01); G06F 21/85 (2013.01);
Abstract

A storage drive includes a first memory that stores first text. A first processor generates a first instruction to decrypt the first text. A cryptographic module includes a second memory, a cryptographic device, a memory module, and a second processor. The second memory is inaccessible to the first processor and stores a cryptographic key. The cryptographic device accesses the second memory to obtain the cryptographic key and based on the first instruction, decrypts the first text. The memory module stores a status of execution of the first instruction by the cryptographic device. The second processor, prior to the cryptographic device decrypting the first text, forwards the first instruction to the cryptographic device and stores the status of execution of the first instruction in the memory module. The memory module is connected between the first and second processors and isolates the first processor from the second processor.


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