The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2016

Filed:

Nov. 15, 2010
Applicants:

Jun Doi, Kanagawa, JP;

Yasushi Negishi, Kanagawa-ken, JP;

Inventors:

Jun Doi, Kanagawa, JP;

Yasushi Negishi, Kanagawa-ken, JP;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 15/173 (2006.01); G06F 15/80 (2006.01); G06F 9/50 (2006.01); H04L 29/08 (2006.01); G06F 7/38 (2006.01);
U.S. Cl.
CPC ...
G06F 15/803 (2013.01); G06F 9/5066 (2013.01); G06F 7/38 (2013.01); H04L 29/08072 (2013.01);
Abstract

Optimally scheduling a plurality of computation processes including all-to-all communications (A2A) among a plurality of nodes (processors) constituting an n-dimensional (a torus or a mesh) network. The plurality of nodes (processors) constituting the network are divided into a communication (computation process) phase (A2A-L) required for all-to-all communications only among a plurality of nodes included in a first subgroup and a communication (computation process) phase (A2A-P) required for all-to-all communications only among a plurality of nodes included in a second subgroup to perform parallel processing with the phases overlapped with each other across a plurality of threads (thread, thread, thread, and thread). It is also possible to perform the parallel processing with respect to a plurality of computation processes such as a fast Fourier transform (FFT) and a transpose (T) (internal transpose).


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