The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2016

Filed:

Apr. 30, 2013
Applicant:

Fujitsu Limited, Kawasaki-shi, Kanagawa, JP;

Inventor:

Naohiro Kiyota, Yokohama, JP;

Assignee:

FUJITSU LIMITED, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2006.01); G06F 9/38 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0875 (2013.01); G06F 9/3834 (2013.01); G06F 9/3861 (2013.01);
Abstract

An arithmetic processing apparatus includes a plurality of processors, each of the processors having an arithmetic unit and a cache memory. The processor includes an instruction port that holds a plurality of instructions accessing data of the cache memory, a first determination unit that validates a first flag when receiving an invalidation request for data in the cache memory, a cache index of a target address and a way ID of the received request match with a cache index of a designated address and a way ID of the load instruction, a second determination unit that validates a second flag when target data is transmitted due to a cache miss, and an instruction re-execution determination unit that instructs re-execution of an instruction subsequent to the load instruction when both the first flag and the second flag are validated at the time of completion of an instruction in the instruction port.


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