The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2016

Filed:

Jun. 15, 2012
Applicants:

Khary J. Alexander, Poughkeepsie, NY (US);

Ilia Averbouch, Haifa, IL;

Ariel J. Birnbaum, Kiryat Motzkin, IL;

Jonathan T. Hsieh, Poughkeepsie, NY (US);

Chung-lung K. Shum, Wappingers Falls, NY (US);

Inventors:

Khary J. Alexander, Poughkeepsie, NY (US);

Ilia Averbouch, Haifa, IL;

Ariel J. Birnbaum, Kiryat Motzkin, IL;

Jonathan T. Hsieh, Poughkeepsie, NY (US);

Chung-Lung K. Shum, Wappingers Falls, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3806 (2013.01); G06F 9/3804 (2013.01);
Abstract

Embodiments relate to collision-based alternate hashing. An aspect includes receiving an incoming instruction address. Another aspect includes determining whether an entry for the incoming instruction address exists in a history table based on a hash of the incoming instruction address. Another aspect includes based on determining that the entry for the incoming instruction address exists in the history table, determining whether the incoming instruction address matches an address tag in the determined entry. Another aspect includes based on determining that the incoming instruction address does not match the address tag in the determined entry, determining whether a collision exists for the incoming instruction address. Another aspect includes based on determining that the collision exists for the incoming instruction address, activating alternate hashing for the incoming instruction address using an alternate hash buffer.


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