The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2016

Filed:

Feb. 28, 2014
Applicant:

Inphi Corporation, Santa Clara, CA (US);

Inventors:

Nirmal Raj Saxena, Santa Clara, CA (US);

Sreenivas Krishnan, Santa Clara, CA (US);

David Wang, Santa Clara, CA (US);

Assignee:

INPHI CORPORATION, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/10 (2006.01); G06F 3/06 (2006.01); G06F 13/40 (2006.01); G06F 12/08 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0688 (2013.01); G06F 3/061 (2013.01); G06F 3/067 (2013.01); G06F 3/0619 (2013.01); G06F 3/0631 (2013.01); G06F 3/0644 (2013.01); G06F 3/0679 (2013.01); G06F 12/0813 (2013.01); G06F 13/4022 (2013.01);
Abstract

Techniques for a massively parallel and memory centric computing system. The system has a plurality of processing units operably coupled to each other through one or more communication channels. Each of the plurality of processing units has an ISMn interface device. Each of the plurality of ISMn interface devices is coupled to an ISMe endpoint connected to each of the processing units. The system has a plurality of DRAM or Flash memories configured in a disaggregated architecture and one or more switch nodes operably coupling the plurality of DRAM or Flash memories in the disaggregated architecture. The system has a plurality of high speed optical cables configured to communicate at a transmission rate of 100 G or greater to facilitate communication from any one of the plurality of processing units to any one of the plurality of DRAM or Flash memories.


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