The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 26, 2016

Filed:

Nov. 10, 2011
Applicants:

Kosuke Tatsumura, Kawasaki, JP;

Atsuhiro Kinoshita, Kamakura, JP;

Hirotaka Nishino, Yokohama, JP;

Masamichi Suzuki, Tokyo, JP;

Yoshifumi Nishi, Yokohama, JP;

Takao Marukame, Tokyo, JP;

Takahiro Kurita, Kawasaki, JP;

Inventors:

Kosuke Tatsumura, Kawasaki, JP;

Atsuhiro Kinoshita, Kamakura, JP;

Hirotaka Nishino, Yokohama, JP;

Masamichi Suzuki, Tokyo, JP;

Yoshifumi Nishi, Yokohama, JP;

Takao Marukame, Tokyo, JP;

Takahiro Kurita, Kawasaki, JP;

Assignee:

Kabushiki Kaisha Toshiba, Minato-ku, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); H04L 12/64 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
H04L 12/6418 (2013.01); G06F 3/0605 (2013.01); G06F 3/0635 (2013.01); G06F 3/0656 (2013.01); G06F 3/0658 (2013.01); G06F 3/0683 (2013.01);
Abstract

According to one embodiment, a storage device includes a plurality of memory nodes. Each of memory nodes includes a plurality of input ports, a plurality of output ports, a selector, a packet controller and a memory. The selector outputs a packet input to the input port to one of the output ports. The packet controller controls the selector. The memory stores data. The memory nodes are mutually connected at the input ports and the output ports. The memory node has an address that is determined by its physical position. The packet controller switches the output port that outputs the packet based on information including at least a destination address of the packet and an address of the memory node having the packet controller when receiving a packet that is not addressed to the memory node having the packet controller.


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