Analogue to digital conversion device

Abstract

An A/D conversion device has an A/D conversion section including A/D conversion units. Each A/D conversion unit has a pulse delay circuit including delay units connected in daisy chain to form a ring delay line. Each delay unit delays a pulse signal by a delay time corresponding to an input voltage. The A/D conversion section counts the number of pulse signals that passed through the delay units during a period counted from a timing when a start signal is switched to an activation level from a non-activation level at a timing when a sampling signal is received. When each two successive timing signals CKi (i=1, 2, . . . and m) have a same specific period. The each two successive timing signals have a different phase shifted by 1/m of the specific period. Each A/D conversion unit receives the timing signal CKas the start signal, and the timing signal CKi+1 (CKm+1=CK) as the sampling signal.