The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 26, 2016
Filed:
Sep. 29, 2014
Applicant:
Texas Instruments Incorporated, Dallas, TX (US);
Inventors:
Suvam Nandi, Bangalore, IN;
Badarish Mohan Subbannavar, Bangalore, IN;
Assignee:
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/00 (2006.01); H03K 19/0185 (2006.01); H03K 19/096 (2006.01); H03K 5/135 (2006.01); H03K 3/037 (2006.01);
U.S. Cl.
CPC ...
H03K 19/0013 (2013.01); H03K 3/0372 (2013.01); H03K 5/135 (2013.01); H03K 19/0002 (2013.01); H03K 19/01855 (2013.01); H03K 19/0966 (2013.01); H03K 19/0016 (2013.01);
Abstract
The disclosure provides an ICG (integrated clock gating) cell that utilizes a low area and a low power latch. The ICG cell includes a first logic gate that receives an enable signal and generates a latch input. A latch is coupled to the first logic gate and receives the latch input and a clock input. The latch includes a tri-state inverter and an inverting logic gate. The tri-state inverter is activated by a control signal generated by the inverting logic gate. A second logic gate receives the control signal and generates a gated clock.