The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 26, 2016

Filed:

Mar. 25, 2014
Applicant:

Marvell World Trade Ltd., St. Michael, BB;

Inventors:

Sehat Sutardja, Los Altos Hills, CA (US);

Poh Boon Leong, Singapore, SG;

Ping Song, Sunnyvale, CA (US);

Nuntha Kumar Krishnasamy Maniam, Cupertino, CA (US);

Assignee:

Marvell World Trade Ltd., St. Michael, BB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/45 (2006.01); H03F 1/22 (2006.01); H03F 3/21 (2006.01); H03F 3/26 (2006.01);
U.S. Cl.
CPC ...
H03F 3/45076 (2013.01); H03F 1/223 (2013.01); H03F 3/21 (2013.01); H03F 3/211 (2013.01); H03F 3/26 (2013.01); H03F 3/265 (2013.01); H03F 3/45475 (2013.01); H03F 2200/537 (2013.01); H03F 2200/541 (2013.01); H03F 2203/45731 (2013.01);
Abstract

A differential power amplifier including a push-pull pair of transistors, a capacitance, a first inductance, and a second inductance. The push-pull pair of transistors includes first and second transistors. The first transistor includes control and output terminals. The second transistor includes input and control terminals. The control terminals of the first and second transistors collectively receive a differential input signal. The output and input terminals collectively provide a differential output signal. The capacitance is connected to the output and input terminals. The first capacitance cancels first harmonics at the output terminal of the first transistor with second harmonics at the input terminal of the second transistor. The first transistor and the first inductance are connected in series between a voltage source and a reference terminal. The second transistor and the second inductance are connected in series between the voltage source and the reference terminal.


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