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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9246014 B1

PDFFull Text
Date of Patent:
Jan. 26, 2016

Filed:

Mar. 16, 2015

Nonvolatile semiconductor memory element, nonvolatile semiconductor memory, and method for operating nonvolatile semiconductor memory element

Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Masao Shingu, Kawasaki, JP;

Jun Fujiki, Yokohama, JP;

Naoki Yasuda, Yokohama, JP;

Koichi Muraoka, Sagamihara, JP;

Assignee:

KABUSHIKI KAISHA TOSHIBA, Minato-ku, JP;

Attorney:

Oblon, McClelland, Maier & Neustadt, L.L.P.

Primary Examiner:

Matthew Reames

Int. Cl.
CPC ...
H01L 27/115 (2006.01); H01L 29/788 (2006.01); H01L 21/28 (2006.01); H01L 29/51 (2006.01); H01L 29/792 (2006.01); G11C 11/40 (2006.01); G11C 16/04 (2006.01); G11C 16/12 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); G11C 16/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/788 (2013.01); G11C 11/40 (2013.01); G11C 16/0408 (2013.01); G11C 16/0466 (2013.01); G11C 16/10 (2013.01); G11C 16/12 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); H01L 21/28282 (2013.01); H01L 27/11521 (2013.01); H01L 27/11556 (2013.01); H01L 27/11582 (2013.01); H01L 29/4234 (2013.01); H01L 29/495 (2013.01); H01L 29/4966 (2013.01); H01L 29/513 (2013.01); H01L 29/517 (2013.01); H01L 29/518 (2013.01); H01L 29/7883 (2013.01); H01L 29/792 (2013.01);
Abstract

According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.

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