The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 26, 2016

Filed:

Jun. 11, 2015
Applicant:

Panasonic Intellectual Property Management Co., Ltd., Osaka, JP;

Inventors:

Kazuhiro Kaibara, Osaka, JP;

Hiroshige Hirano, Toyama, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 23/482 (2006.01); H01L 29/778 (2006.01); H01L 29/06 (2006.01); H01L 23/00 (2006.01); H01L 29/66 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5283 (2013.01); H01L 23/4824 (2013.01); H01L 24/05 (2013.01); H01L 29/0696 (2013.01); H01L 29/7787 (2013.01); H01L 24/45 (2013.01); H01L 24/48 (2013.01); H01L 29/2003 (2013.01); H01L 29/66462 (2013.01); H01L 2224/02166 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05027 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05567 (2013.01); H01L 2224/05573 (2013.01); H01L 2224/05639 (2013.01); H01L 2224/05644 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05655 (2013.01); H01L 2224/45015 (2013.01); H01L 2224/45124 (2013.01); H01L 2224/45144 (2013.01); H01L 2224/45147 (2013.01); H01L 2224/48639 (2013.01); H01L 2224/48644 (2013.01); H01L 2224/48647 (2013.01); H01L 2224/48655 (2013.01); H01L 2224/48739 (2013.01); H01L 2224/48744 (2013.01); H01L 2224/48747 (2013.01); H01L 2224/48755 (2013.01); H01L 2224/48839 (2013.01); H01L 2224/48844 (2013.01); H01L 2224/48847 (2013.01); H01L 2224/48855 (2013.01);
Abstract

A semiconductor device includes a first wiring layer stacked over element electrodes above a silicon substrate and a second wiring layer stacked over the first wiring layer. The first wiring layer includes first source electrode wires and first drain electrode wires. The second wiring layer includes second source electrode wires and second drain electrode wires. The first wiring layer includes a first region and second regions. In the first region, each of the first source electrode wires and the first drain electrode wires is continuous. In each of the second regions, each of the first source electrode wires and the first drain electrode wires is discontinuous. Second source electrode wires and second drain electrode wires are arranged to alternately over the first regions and the second regions in one direction. External connection terminals are not connected over the second regions, and are connected over the first regions.


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