The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 26, 2016

Filed:

Nov. 05, 2014
Applicant:

Alpha and Omega Semiconductor (Cayman) Ltd., Sunnyvale, CA (US);

Inventors:

Yan Huo, Shanghai, CN;

Zhi Qiang Niu, Santa Clara, CA (US);

Ming-Chen Lu, Shanghai, CN;

Hongtao Gao, Shanghai, CN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49562 (2013.01); H01L 21/4875 (2013.01); H01L 21/565 (2013.01); H01L 23/3114 (2013.01); H01L 23/49513 (2013.01);
Abstract

A semiconductor package includes a lead frame having a die paddle and a plurality of leads connected to die paddle, where each lead has a lead surface parallel to die paddle and is a continuous extension bending upward from die paddle. A semiconductor chip is mounted on die paddle, where drain metal layer covering a first surface of chip is connected to die paddle, and source metal layer and gate metal layer are located on a second surface opposite to first surface with gate metal layer located at one corner of the second surface. A source metal plate and a gate metal plate are attached on source metal layer and gate metal layer respectively. A molding layer covers lead frame, semiconductor chip, source metal plate and gate metal plate, where lead surface, top surfaces of source metal plate and gate metal plate are exposed from top surface of molding layer.


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