The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 26, 2016

Filed:

Jan. 30, 2013
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Gerald K. Bartley, Rochester, MN (US);

Charles L. Johnson, Rochester, MN (US);

John E. Kelly, III, Poughquag, NY (US);

Joseph Kuczynski, Rochester, MN (US);

David R. Motschman, Rochester, MN (US);

Arvind K Sinha, Rochester, MN (US);

Kevin A. Splittstoesser, Stewartville, MN (US);

Timothy A. Tofil, Rochester, MN (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/34 (2006.01); H01L 23/00 (2006.01); H01L 23/373 (2006.01); H01L 23/36 (2006.01); H01L 23/42 (2006.01); H01L 23/427 (2006.01); H01L 21/48 (2006.01); H01L 25/065 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/00 (2013.01); H01L 21/4882 (2013.01); H01L 23/36 (2013.01); H01L 23/373 (2013.01); H01L 23/42 (2013.01); H01L 23/4275 (2013.01); H01L 25/0657 (2013.01); H01L 23/481 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06589 (2013.01); H01L 2924/0002 (2013.01);
Abstract

The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes a thermal interface material pad between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip, and a heat removal device thermally connected to the thermal interface material pad.


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