The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 26, 2016

Filed:

Dec. 17, 2013
Applicant:

Spansion Llc, Sunnyvale, CA (US);

Inventor:

Masanori Onodera, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 23/10 (2006.01); H01L 29/40 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 21/563 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15331 (2013.01); H01L 2924/18161 (2013.01); H01L 2924/19107 (2013.01);
Abstract

The present invention provides a semiconductor device with an improved yield ratio and reduced height and manufacturing cost; and a method of manufacturing the semiconductor device. According to an aspect of the present invention, there is provided a semiconductor device including a substrate, a semiconductor element that is flip-chip connected to the substrate, and a molding portion that seals the semiconductor element. The side surfaces of the semiconductor element are enclosed by the molding portion. An upper surface of the semiconductor element is not enclosed by the molding portion. Damage to the side surfaces of the semiconductor element caused by an external impact when the semiconductor device is stored is minimized, because the molding portion protects the side surfaces of the semiconductor element. Accordingly, the yield ratio of the semiconductor device is improved. The height of the semiconductor device can also be reduced since the upper surface of the semiconductor element is not enclosed with the molding portion.


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