Semiconductor chip including digital logic circuit including at least nine linear-shaped conductive structures collectively forming gate electrodes of at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods

Abstract

At least nine linear-shaped conductive structures (LCS's) are positioned in accordance with a first pitch. Five of the at least nine LCS's collectively form three transistors of a first transistor type and three transistors of a second transistor type. Transistors of the first transistor type are collectively separated from transistors of the second transistor type by an inner region. Two transistors of the first transistor type and two transistors of the second transistor type are cross-coupled transistors. Each of four LCS's corresponding to the cross-coupled transistors has a respective electrical connection area located within the inner region. The two LCS's corresponding to the two transistors of the first transistor type of the cross-coupled transistors have electrical connections areas that are not aligned with each other. The four LCS's corresponding to the cross-coupled transistors include at least two different inner extension distances beyond their respective electrical connection areas.