The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9241410 B1

PDF
Full Text
Expired
Date of Patent:
Jan. 19, 2016

Filed:

May. 31, 2012
Applicants:

Saori Ishigaki, Osaka, JP;

Jun Ishii, Osaka, JP;

Yoshito Fujimura, Osaka, JP;

Yuu Sugimoto, Osaka, JP;

Inventors:

Saori Ishigaki, Osaka, JP;

Jun Ishii, Osaka, JP;

Yoshito Fujimura, Osaka, JP;

Yuu Sugimoto, Osaka, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/16 (2006.01); H05K 1/18 (2006.01); H05K 3/32 (2006.01); G11B 5/48 (2006.01);
U.S. Cl.
CPC ...
H05K 1/189 (2013.01); H05K 3/321 (2013.01); G11B 5/484 (2013.01); G11B 5/4853 (2013.01); G11B 5/4873 (2013.01); H05K 2201/0385 (2013.01); H05K 2201/053 (2013.01); H05K 2201/09072 (2013.01); H05K 2201/10083 (2013.01);
Abstract

A wired circuit board includes an insulating layer, and a conductive layer including a wire covered with the insulating layer and a terminal continued to the wire to electrically connect the wire to an electronic element. The insulating layer is formed with an insulating opening exposing the terminal, and the terminal is formed in a pattern which is indented in a thickness direction.


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Ishigaki, Saori. (2016). Wired circuit board and producing method thereof (U.S. Patent No. 9241410). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9241410

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