The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 19, 2016
Filed:
Mar. 11, 2013
Applicants:
Kazuyuki Tanimura, Irvine, CA (US);
Nikil Dutt, Irvine, CA (US);
Inventors:
Kazuyuki Tanimura, Irvine, CA (US);
Nikil Dutt, Irvine, CA (US);
Assignee:
THE REGENTS OF THE UNIVERSITY OF CALIFORNIA, Oakland, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/00 (2006.01); H03K 19/003 (2006.01); H03K 19/096 (2006.01);
U.S. Cl.
CPC ...
H03K 19/003 (2013.01); H03K 19/00392 (2013.01); H03K 19/096 (2013.01);
Abstract
Homogenous dual-rail logic for DPA attack resistive secure circuit design is disclosed. According to one embodiment, an HDRL circuit comprises a primary cell and a complementary cell, wherein the complementary cell is an identical duplicate of the primary cell. The HURL circuit comprises a first set of inputs and a second set of inputs, wherein the second set of inputs are a negation of the first set of inputs. The HURL circuit has a differential power at a level that is resistive to DPA attacks.