The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 19, 2016
Filed:
Jan. 16, 2013
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, KR;
Inventors:
Hyun-Seok Na, Hwaseong-si, KR;
Ji-Hwon Lee, Suwon-si, KR;
Joong-Shik Shin, Yongin-si, KR;
Chang-Sun Lee, Seoul, KR;
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/764 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 21/762 (2006.01); H01L 27/115 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66477 (2013.01); H01L 21/28273 (2013.01); H01L 21/764 (2013.01); H01L 21/76224 (2013.01); H01L 21/76229 (2013.01); H01L 27/1157 (2013.01); H01L 27/11519 (2013.01); H01L 27/11524 (2013.01); H01L 27/11565 (2013.01);
Abstract
Provided is a fabricating method of a nonvolatile memory. The fabricating method includes forming a plurality of gates extending in a first direction on a substrate to be adjacent to each other, forming a gap-fill layer filling at least a portion of a space between the plurality of gates, forming a supporter pattern supporting the plurality of gates on the plurality of gates and the gap-fill layer, and forming an air gap in the space between the plurality of gates by removing the gap-fill layer.