The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 19, 2016

Filed:

Jul. 15, 2011
Applicants:

Hiroki Wakimoto, Matsumoto, JP;

Masaaki Ogino, Matsumoto, JP;

Inventors:

Hiroki Wakimoto, Matsumoto, JP;

Masaaki Ogino, Matsumoto, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kawasaki-Shi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/332 (2006.01); H01L 29/66 (2006.01); H01L 21/761 (2006.01); H01L 21/78 (2006.01); H01L 21/308 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66325 (2013.01); H01L 21/3083 (2013.01); H01L 21/761 (2013.01); H01L 21/78 (2013.01); H01L 29/0646 (2013.01); H01L 29/0661 (2013.01); H01L 29/66333 (2013.01); H01L 29/0619 (2013.01);
Abstract

A method includes forming on a first main surface of a semiconductor wafer of a first conduction type, a gate electrode of a semiconductor element, an edge termination region for forming a breakdown voltage of the semiconductor element, and a first semiconductor region of a second conduction type which surrounds the semiconductor element and the edge termination region. A groove may be formed to reach the first semiconductor region from a second main surface of the semiconductor wafer. The groove is formed so that a portion of the semiconductor wafer, that forms an outer circumferential end of the semiconductor wafer, remains and the groove is further towards a center of the semiconductor wafer than the outer circumferential end. A third semiconductor region of the second conduction type is on a side wall of the groove and electrically connects the first semiconductor region and a second semiconductor region.


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