The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 19, 2016

Filed:

Oct. 01, 2013
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Venkateswara Reddy P, Bangalore, IN;

Vinayak Ghatawade, Bangalore, IN;

Rajat Chauhan, Dehradun, IN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H02H 9/04 (2006.01); H02H 3/00 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0248 (2013.01);
Abstract

An input/output (IO) circuit is provided that reduces stress on a driver without using an additional reference voltage. The IO circuit receives an overshoot voltage and an undershoot voltage in a receive mode. The IO circuit includes a driver circuit. The driver circuit includes an NMOS transistor coupled to a PMOS transistor. A pad is coupled to the driver circuit. A PMOS protect circuit is coupled to the driver circuit and the pad. An NMOS protect circuit is coupled to the driver circuit and the pad. The NMOS protect circuit is configured to be activated only for a duration of the overshoot voltage received at the pad during the receive mode and the PMOS protect circuit is configured to be activated only for a duration of the undershoot voltage received at the pad during the receive mode.


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