The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 12, 2016

Filed:

Mar. 03, 2014
Applicant:

Samsung Display Co., Ltd., Yongin, Gyeonggi-Do, KR;

Inventors:

Jae-Neung Kim, Yongin, KR;

Yu-Gwang Jeong, Yongin, KR;

Sang-Gab Kim, Yongin, KR;

Su-Bin Bae, Yongin, KR;

Shin-Il Choi, Yongin, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1343 (2006.01); G02F 1/1362 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1225 (2013.01); G02F 1/134309 (2013.01); G02F 1/136213 (2013.01); H01L 27/1248 (2013.01); H01L 27/1255 (2013.01); H01L 27/1259 (2013.01);
Abstract

A display apparatus includes: a substrate defining transistor and wiring areas; a thin film transistor in the transistor area and including a gate electrode, an active layer, and source and drain electrodes; an etch prevention layer in the transistor area, absent in the wiring area and covering the active layer, and first and second contact holes defined in the etch prevention layer and through which the active layer is electrically coupled to the source and drain electrodes; a first wiring layer in the wiring area; a first insulating layer which covers the gate electrode and the first wiring layer, and a third contact hole defined in the first insulating layer in the wiring area and exposing the first wiring layer; and a second wiring layer on the first insulating layer and in the wiring area, and electrically coupled to the first wiring layer via the third contact hole.


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