The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 12, 2016

Filed:

Dec. 16, 2011
Applicants:

Christian René Bonhôte, San Jose, CA (US);

Jeffrey S. Lille, Sunnyvale, CA (US);

Ricardo Ruiz, Santa Clara, CA (US);

Georges Gibran Siddiqi, San Jose, CA (US);

Inventors:

Christian René Bonhôte, San Jose, CA (US);

Jeffrey S. Lille, Sunnyvale, CA (US);

Ricardo Ruiz, Santa Clara, CA (US);

Georges Gibran Siddiqi, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/70 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28052 (2013.01); H01L 29/665 (2013.01); H01L 29/78 (2013.01); H01L 21/823814 (2013.01); H01L 21/823828 (2013.01);
Abstract

An integrated circuit has a doped silicon semiconductor with regions of insulators and bare silicon. The bare silicon regions are isolated from other bare silicon regions. A semiconductor device on the doped silicon semiconductor has at least two electrical connections to form regions of patterned metal. A metal is electroplated directly on each of the regions of patterned metal to form plated connections without a seed layer. A self-aligned silicide is located under each plated connection, formed by annealing, for the regions of plated metal on bare silicon.


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