The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 12, 2016

Filed:

Sep. 12, 2012
Applicants:

Srinivasa Raghavan Sridhara, Plano, TX (US);

Raviprakash Suryanarayana Rao, Dallas, TX (US);

Inventors:
Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 7/08 (2006.01); G11C 7/22 (2006.01); G11C 29/50 (2006.01); G11C 11/41 (2006.01);
U.S. Cl.
CPC ...
G11C 7/08 (2013.01); G11C 7/227 (2013.01); G11C 29/50012 (2013.01); G11C 11/41 (2013.01);
Abstract

An embodiment of the invention discloses a method for writing concurrently a binary logical value to one or more dummy memory cells in a dummy bit line pair. A diode is electrically connected between a power supply and the positive power supply line connected to the dummy memory cells. The binary logical value is then driven on to the dummy bit line pair. Next, one or more dummy word lines are driven to a logical high allowing selected dummy memory cells to be written with the binary logical value. After the selected dummy memory cells have been written to, the one or more dummy word lines are driven to a logical low. Next the diode is disabled by turning on a PFET connected between the power supply and the positive power supply line. Turning on the PFET also electrically connects the power supply to the positive power supply line.


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