The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 12, 2016

Filed:

Oct. 01, 2014
Applicant:

Entropic Communications, Llc, Carlsbad, CA (US);

Inventors:

Raed Moughabghab, Encinitas, CA (US);

Branislav Petrovic, La Jolla, CA (US);

Michael Scott, Austin, TX (US);

Assignee:

Entropic Communications, LLC., Carlsbad, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5081 (2013.01); G06F 17/505 (2013.01); G06F 2217/78 (2013.01);
Abstract

A method and an apparatus from such method for designing an integrated circuit (IC) that mitigates the effects of process, voltage, and temperature dependent characteristics on the fabrication of advanced IC's but provides high die yields, lower power usage, and faster circuits. Conventional design process takes into account power supply voltage Vdd as a variable that must be considered in a skewed corner analysis. The disclosure teaches that the IC design process can be substantially simplified by essentially factoring out voltage based variations in corner lot analysis for IC designs that include dynamic voltage scaling circuitry, because each fabricated IC die of an IC design having dynamic voltage scaling can individually adjust the applied supply voltage Vdd within a range to offset local process-induced variations in the performance of that specific IC die.


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