The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 12, 2016

Filed:

Dec. 21, 2012
Applicant:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Inventors:

Lisa R. Hsu, Kirkland, WA (US);

Gabriel H. Loh, Bellevue, WA (US);

Michael Ignatowski, Austin, TX (US);

Michael J. Schulte, Austin, TX (US);

Nuwan S. Jayasena, Sunnyvale, CA (US);

James M. O'Connor, Austin, TX (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 12/10 (2006.01); G06F 11/20 (2006.01); G06F 11/16 (2006.01);
U.S. Cl.
CPC ...
G06F 12/10 (2013.01); G06F 11/2094 (2013.01); G06F 11/1666 (2013.01);
Abstract

A system, method, and memory device embodying some aspects of the present invention for remapping external memory addresses and internal memory locations in stacked memory are provided. The stacked memory includes one or more memory layers configured to store data. The stacked memory also includes a logic layer connected to the memory layer. The logic layer has an Input/Output (I/O) port configured to receive read and write commands from external devices, a memory map configured to maintain an association between external memory addresses and internal memory locations, and a controller coupled to the I/O port, memory map, and memory layers, configured to store data received from external devices to internal memory locations.


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