The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 12, 2016
Filed:
Apr. 15, 2015
Fujitsu Limited, Kawasaki-shi, Kanagawa, JP;
Shigeaki Sekiguchi, Zama, JP;
Nobuhiro Imaizumi, Atsugi, JP;
Toshiya Akamatsu, Zama, JP;
Shinji Tadaki, Atsugi, JP;
Akinori Hayakawa, Sagamihara, JP;
FUJITSU LIMITED, Kawasaki, JP;
Abstract
An optical device includes: an optical integrated circuit chip that comprises an optical integrated circuit and an optical interface connected thereto; an electronic circuit chip that comprises an electronic circuit connected to the optical integrated circuit; a through wiring board that comprises a through wiring connected to the electronic circuit chip; a first bump that connects the optical integrated circuit and the electronic circuit between the optical integrated circuit chip and the electronic circuit chip; a second bump that connects the electronic circuit and the through wiring between the electronic circuit chip and the through wiring board; and a third bump connected to an end portion on an opposite side to the second bump of the through wiring. The optical integrated circuit chip and the through wiring board are disposed on a side of a first main surface of the electronic circuit chip. A first distance between the first main surface and a second main surface of the optical integrated circuit chip, the second main surface being on an opposite side to the electronic circuit chip, is equal to or smaller than a second distance between the first main surface and a vertex of the third bump, the vertex being on an opposite side to the electronic circuit chip.