The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2016

Filed:

Jan. 18, 2013
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventor:

Erkan Bilhan, Dallas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02J 4/00 (2006.01); G06F 1/26 (2006.01); G06F 21/86 (2013.01);
U.S. Cl.
CPC ...
H02J 4/00 (2013.01); G06F 1/26 (2013.01); G06F 21/86 (2013.01); Y10T 307/383 (2015.04);
Abstract

This invention is a System On a Chip (SOC) requiring two tamper resistant externally generated power supplies. A first, higher power supply powers I/O and analog circuits. A second, lower power supply powers digital circuits and memory. A first voltage monitor circuit powered by said first power supply generates a first output signal when the first power supply is below an operational limit high level. A second voltage monitor circuit powered by said first power supply indicates when the second power supply is above an operational high limit level. A power switch is controlled by the first voltage monitor circuit. This power switch connects the second power supply and second load when closed and isolates them when open. Thus the memory cannot be accessed when the I/O and analog power supply is out of specification.


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