The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2016

Filed:

Jan. 16, 2014
Applicants:

Dmitry Veinger, Zikhron Ya'akov, IL;

Assaf Lahav, Binyamina, IL;

Omer Katz, Nofit, IL;

Ruthie Shima-edelstein, Haifa, IL;

Inventors:

Dmitry Veinger, Zikhron Ya'akov, IL;

Assaf Lahav, Binyamina, IL;

Omer Katz, Nofit, IL;

Ruthie Shima-Edelstein, Haifa, IL;

Assignee:

TOWER SEMICONDUCTOR LTD., Migdal Haemek, IL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01); H01L 27/148 (2006.01);
U.S. Cl.
CPC ...
H01L 27/14698 (2013.01); H01L 27/14812 (2013.01);
Abstract

Some demonstrative embodiments include devices and/or methods of gettering on silicon on insulator (SOI) substrate. For example, a complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) may include a plurality of pixels arranged on a wafer, a pixel of the pixels including: a silicon active area; at least one non-silicided leakage-sensitive component formed on the active area, the leakage-sensitive component is sensitive to metal contaminants; a non-leakage-sensitive area formed on the active area, the non-leakage-sensitive area surrounding the leakage-sensitive component; and at least one silicided gettering region formed on the non-leakage-sensitive area to trap the metal contaminants.


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