The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2016

Filed:

Mar. 30, 2015
Applicant:

Renesas Electronics Corporation, Kanagawa, JP;

Inventor:

Nobuo Tsuboi, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/11 (2006.01); H01L 21/8244 (2006.01); H01L 27/02 (2006.01); H01L 27/105 (2006.01); H01L 21/768 (2006.01); H01L 23/482 (2006.01); H01L 23/50 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1104 (2013.01); H01L 21/76808 (2013.01); H01L 23/4827 (2013.01); H01L 23/50 (2013.01); H01L 27/0207 (2013.01); H01L 27/105 (2013.01); H01L 27/11 (2013.01); H01L 27/1116 (2013.01); H01L 2924/0002 (2013.01); Y10S 257/903 (2013.01);
Abstract

A semiconductor device in which wirings are formed adequately and electrical couplings are made properly in an SRAM memory cell. In the SRAM memory cell of the semiconductor device, a via to be electrically coupled to a third wiring as a word line is directly coupled to a contact plug electrically coupled to the gate wiring part of an access transistor. Also, another via to be electrically coupled to the third wiring as the word line is directly coupled to a contact plug electrically coupled to the gate wiring part of another access transistor.


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